01774nam a2200217Ia 4500 CTU_157766 210402s9999 xx 000 0 und d 70.36 621.3815 F949 Fujita, Masahiro Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, Mukul Prasad Amsterdam Morgan Kaufmann Publishers 2008 This book will explain how to verify SoC logic designs using "formal" and "semi-formal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional" verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. Integrated circuits,Formal methods (Computer science),Mạch tích hợp,Phương pháp hình thức (Khoa học máy tính),Systems on a chip,Hệ thống trên một chip Verification,Mã xác nhận,Testing,Thử nghiệm Trọng Hải Trung tâm Học liệu Trường Đại học Cần Thơ