http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Nội dung cuốn giáo trình mô tả bốn vấn đề chính được tập trung ở bốn chương. Thứ nhất là tổng quan về thiết kế và chế tạo IC. Thứ hai là cách thiết kế layout của IC. Thứ 3 là giới thiệu một số họ IC có khả năng lập trình được. Cuối cùng là giới thiệu ngôn ngữ mô tả phần cứng - VHDL. Sau khi học xong chương 1, sinh viên có khả năng trả lời các câu hỏi: 1. Nêu qui trình các bước thiết kế vi mạch cho thiết kế số? 2. Các bước cơ bản khi chế tạo IC? 3. Khái niệm wafer là gì? 4. Nêu chi tiết các quá trình xử lý wafer? với chương 2, sinh viên có khả năng trả lời các câu hỏi: 1. Thế nào là vật liệu dẫn điện, vật liệu cách điện và vật liệu bán dẫn? 2. Vật liệu loại N là gì, người ta tạo ra vật liệu loại N như thế nào? 3. Vật liệu loại P là gì, người ta tạo ra vật liệu loại P như thế nào? 4. Tiếp giáp PN là gì, người ta tạo ra tiếp giáp PN như thế nào? 5. Làm thế nào để phân cực cho mối nối PN, khi nào thì mối nối ON được phân cực thuận và phân cực nghịch? 6. Hiệu ứng là gì? 7. Tại sao người ta phải cách ly FET và cách ly FET khi chế tạo được thực hiện như thế nào? 8. Kết nối N Well và kết nối nền là gì? 9. Cách người ta xây dựng mạch logic từ transistor MOS như thế nào? 10. Hãy xây dựng mạch logic cổng NOT và cổng NAND có hai ngõ vào tín hiệu là A và B?....
Mạch tích hợp (Integrated circuit - IC)