A Study of High-Performance Frequency Synthesizer Based on Digital Bang-Bang Phase-Locked Loop for Wireless Applications
Chapter 1. Fractional-N Digital Bang-Bang PLLs; Chapter 2. Frequency Aid Technique; Chapter 3. LMS Calibration Loop; ...
Đã lưu trong:
| Príomhúdar: | Vo Tuan Minh |
|---|---|
| Teanga: | eng |
| Foilsithe: |
Politecnico di Milano
|
| Rochtain Ar Líne: | https://dlib.udn.vn/module/chi-tiet-sach?RecordID=2796 |
| Clibeanna: |
Cuir Clib Leis
Gan Chlibeanna, Bí ar an gcéad duine leis an taifead seo a chlibeáil!
|
| Thư viện lưu trữ: | Trung tâm Công nghệ thông tin và Học liệu số, Đại học Đà Nẵng |
|---|
Míreanna Comhchosúla
-
Phase-locked loop synthesizer simulation
le: Bianchi, Giovanni
Foilsithe: (2005) -
Phase-locked loop synthesizer simulation
le: Bianchi, Giovanni
Foilsithe: (2005) -
Phase-locked loop synthesizer simulation /
le: Bianchi, Giovanni.
Foilsithe: (2005) -
Phase-locked loop synthesizer simulation
le: Bianchi, Giovanni.
Foilsithe: (2005) -
A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel
le: Purkayastha, Basab Bijoy, et al.
Foilsithe: (2015)