APA aipamena

Truong, Q. D., Duong, N. P., & Lee, H. (2024). Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard. IEEE.

Chicago Style aipamena

Truong, Quang Dang, Ngoc Phap Duong, và Hanho Lee. Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard. IEEE, 2024.

MLA aipamena

Truong, Quang Dang, Ngoc Phap Duong, và Hanho Lee. Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard. IEEE, 2024.