A design of 32KB SRAM combining row and column redundancy
में बचाया:
| भाषा: | vie |
|---|---|
| ऑनलाइन पहुंच: | https://dlib.udn.vn/module/chi-tiet-sach?RecordID=9178 |
| टैग : |
टैग जोड़ें
कोई टैग नहीं, इस रिकॉर्ड को टैग करने वाले पहले व्यक्ति बनें!
|
| Thư viện lưu trữ: | Trung tâm Công nghệ thông tin và Học liệu số, Đại học Đà Nẵng |
|---|
समान संसाधन
- Mean - a supporting tool for analysing and designing SRAM cells
-
Logic-based design of groundwater monitoring network for redundancy reduction /
द्वारा: Dhar, Anirban. -
Development of a calculation program to design wagon wheelsets based on the reliability of redundant joints
द्वारा: Đỗ, Đức Tuấn, और अन्य
प्रकाशित: (2024) -
Phố Cannery Row
द्वारा: Steinbeck, John
प्रकाशित: (2018) -
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
द्वारा: Pavlov, Andrei, और अन्य
प्रकाशित: (2020)