Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard
IEEE Access, Vol 12; pp: 32395-32407.
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2024
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oai:elib.vku.udn.vn:123456789-40132024-07-30T08:52:45Z Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard Truong, Quang Dang Duong, Ngoc Phap Lee, Hanho Post-quantum cryptography (PQC) module-lattice-based digital signature standard (ML-DSA) crystals-Dilithium lattice-based cryptography (LBC) number theoretic transform (NTT) IEEE Access, Vol 12; pp: 32395-32407. The rapid advancement of powerful quantum computers poses a significant security risk to current public-key cryptosystems, which heavily rely on the computational complexity of problems such as discrete logarithms and integer factorization. As a result, CRYSTALS-Dilithium, a lattice-based digital signature scheme with the potential to be an alternative algorithm that can withstand both quantum and classical attacks, has been standardized as ML-DSA after NIST Post-Quantum Cryptography competition. While prior studies have proposed hardware designs to accelerate this cryptosystem, there is room for further optimization in the tradeoff between performance and hardware consumption. This paper addresses these limitations by presenting an efficient low-latency hardware architecture for ML-DSA, leveraging optimized timing schedules for its three main algorithms. The hardware implementation enables runtime switching main operations in ML-DSA with various security levels. We design flexible arithmetic and hash modules tailored for ML-DSA, the most time-consuming submodules and key determinants of the scheme implementation. Combined with efficient operation scheduling to maximize the utilized time of submodules, our design achieves the best latency among FPGA-based implementations, outperforming state-of-the-art works by 1.27 $\sim 2.58\times $ in terms of the area-time tradeoff metric. Therefore, the proposed hardware architecture demonstrates its practical applicability for digital signature cryptosystems in post-quantum era. 2024-07-30T08:52:40Z 2024-07-30T08:52:40Z 2024-02 Working Paper 2169-3536 10.1109/ACCESS.2024.3370470 https://elib.vku.udn.vn/handle/123456789/4013 vi application/pdf IEEE |
| institution |
Trường Đại học Công nghệ Thông tin và Truyền thông Việt Hàn - Đại học Đà Nẵng |
| collection |
DSpace |
| language |
Vietnamese |
| topic |
Post-quantum cryptography (PQC) module-lattice-based digital signature standard (ML-DSA) crystals-Dilithium lattice-based cryptography (LBC) number theoretic transform (NTT) |
| spellingShingle |
Post-quantum cryptography (PQC) module-lattice-based digital signature standard (ML-DSA) crystals-Dilithium lattice-based cryptography (LBC) number theoretic transform (NTT) Truong, Quang Dang Duong, Ngoc Phap Lee, Hanho Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard |
| description |
IEEE Access, Vol 12; pp: 32395-32407. |
| format |
Working Paper |
| author |
Truong, Quang Dang Duong, Ngoc Phap Lee, Hanho |
| author_facet |
Truong, Quang Dang Duong, Ngoc Phap Lee, Hanho |
| author_sort |
Truong, Quang Dang |
| title |
Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard |
| title_short |
Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard |
| title_full |
Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard |
| title_fullStr |
Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard |
| title_full_unstemmed |
Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard |
| title_sort |
efficient low-latency hardware architecture for module-lattice-based digital signature standard |
| publisher |
IEEE |
| publishDate |
2024 |
| url |
https://elib.vku.udn.vn/handle/123456789/4013 |
| _version_ |
1849201508465246208 |