Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard

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Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard

IEEE Access, Vol 12; pp: 32395-32407.

Wedi'i Gadw mewn:

Manylion Llyfryddiaeth
Prif Awduron:	Truong, Quang Dang, Duong, Ngoc Phap, Lee, Hanho
Fformat:	Bài viết
Iaith:	Vietnamese
Cyhoeddwyd:	IEEE 2024
Pynciau:	Post-quantum cryptography (PQC) module-lattice-based digital signature standard (ML-DSA) crystals-Dilithium lattice-based cryptography (LBC) number theoretic transform (NTT)
Mynediad Ar-lein:	https://elib.vku.udn.vn/handle/123456789/4013
Tagiau:	Ychwanegu Tag Dim Tagiau, Byddwch y cyntaf i dagio'r cofnod hwn!

Thư viện lưu trữ:	Trường Đại học Công nghệ Thông tin và Truyền thông Việt Hàn - Đại học Đà Nẵng

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