Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design. Incorporating simple methods...
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| Định dạng: | Sách |
| Ngôn ngữ: | English |
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CRC Press
2009
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| Truy cập trực tuyến: | http://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/1612 |
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oai:scholar.dlu.edu.vn:DLU123456789-16122009-12-04T02:25:25Z Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC Coppola, Marcello Grammatikakis, Miltos Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design. Incorporating simple methods with easy-to-understand examples, this book considers a wealth of important theoretical and practical topics, such as technological deep sub-micron effects, generic NoC components, topological properties, embeddings of common communication patterns, and system-level design. A complementary CD-ROM features a practical NoC training approach based on the award-winning OCCN environment. 2009-12-04T02:25:25Z 2009-12-04T02:25:25Z 2008 Book http://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/1612 en application/rar CRC Press |
| institution |
Thư viện Trường Đại học Đà Lạt |
| collection |
Thư viện số |
| language |
English |
| description |
Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design. Incorporating simple methods with easy-to-understand examples, this book considers a wealth of important theoretical and practical topics, such as technological deep sub-micron effects, generic NoC components, topological properties, embeddings of common communication patterns, and system-level design. A complementary CD-ROM features a practical NoC training approach based on the award-winning OCCN environment. |
| format |
Book |
| author |
Coppola, Marcello Grammatikakis, Miltos |
| spellingShingle |
Coppola, Marcello Grammatikakis, Miltos Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC |
| author_facet |
Coppola, Marcello Grammatikakis, Miltos |
| author_sort |
Coppola, Marcello |
| title |
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC |
| title_short |
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC |
| title_full |
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC |
| title_fullStr |
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC |
| title_full_unstemmed |
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC |
| title_sort |
design of cost-efficient interconnect processing units: spidergon stnoc |
| publisher |
CRC Press |
| publishDate |
2009 |
| url |
http://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/1612 |
| _version_ |
1757665458915377152 |