Multi-Net Optimization of VLSI Interconnect

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addres...

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Những tác giả chính:	Moiseev, Konstantin, Kolodny, Avinoam, Wimer, Shmuel
Định dạng:	Sách
Ngôn ngữ:	English
Được phát hành:	Springer 2015
Những chủ đề:	Interconnects Integrated circuit technology Mechanical
Truy cập trực tuyến:	https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/58266
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spelling	oai:scholar.dlu.edu.vn:DLU123456789-582662023-11-11T06:06:07Z Multi-Net Optimization of VLSI Interconnect Moiseev, Konstantin Kolodny, Avinoam Wimer, Shmuel Interconnects Integrated circuit technology Mechanical This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits. 2015-09-15T01:55:57Z 2015-09-15T01:55:57Z 2015 Book ISBN 978-1-4614-0821-5 https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/58266 en application/pdf Springer
institution	Thư viện Trường Đại học Đà Lạt
collection	Thư viện số
language	English
topic	Interconnects Integrated circuit technology Mechanical
spellingShingle	Interconnects Integrated circuit technology Mechanical Moiseev, Konstantin Kolodny, Avinoam Wimer, Shmuel Multi-Net Optimization of VLSI Interconnect
description	This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.
format	Book
author	Moiseev, Konstantin Kolodny, Avinoam Wimer, Shmuel
author_facet	Moiseev, Konstantin Kolodny, Avinoam Wimer, Shmuel
author_sort	Moiseev, Konstantin
title	Multi-Net Optimization of VLSI Interconnect
title_short	Multi-Net Optimization of VLSI Interconnect
title_full	Multi-Net Optimization of VLSI Interconnect
title_fullStr	Multi-Net Optimization of VLSI Interconnect
title_full_unstemmed	Multi-Net Optimization of VLSI Interconnect
title_sort	multi-net optimization of vlsi interconnect
publisher	Springer
publishDate	2015
url	https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/58266
_version_	1782546875186937856

Multi-Net Optimization of VLSI Interconnect

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