Low Power Interconnect Design

Low Power Interconnect Design

This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the tot...

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Chi tiết về thư mục
Tác giả chính: Saini, Sandeep
Định dạng: Sách
Ngôn ngữ:English
Được phát hành: Springer 2015
Những chủ đề:
Interconnects
Design
Circuits
Systems
Truy cập trực tuyến:https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/59133
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Thư viện lưu trữ: Thư viện Trường Đại học Đà Lạt
id oai:scholar.dlu.edu.vn:DLU123456789-59133
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spelling oai:scholar.dlu.edu.vn:DLU123456789-591332023-11-11T06:30:43Z Low Power Interconnect Design Saini, Sandeep Interconnects Design Circuits Systems This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses. 2015-11-05T02:40:49Z 2015-11-05T02:40:49Z 2015 Book 978-1-4614-1323-3 https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/59133 en application/pdf Springer
institution Thư viện Trường Đại học Đà Lạt
collection Thư viện số
language English
topic Interconnects
Design
Circuits
Systems
spellingShingle Interconnects
Design
Circuits
Systems
Saini, Sandeep
Low Power Interconnect Design
description This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.
format Book
author Saini, Sandeep
author_facet Saini, Sandeep
author_sort Saini, Sandeep
title Low Power Interconnect Design
title_short Low Power Interconnect Design
title_full Low Power Interconnect Design
title_fullStr Low Power Interconnect Design
title_full_unstemmed Low Power Interconnect Design
title_sort low power interconnect design
publisher Springer
publishDate 2015
url https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/59133
_version_ 1819783015009615872

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