New Data Structures and Algorithms for Logic Synthesis and Verification

Côd QR

New Data Structures and Algorithms for Logic Synthesis and Verification

Wedi'i Gadw mewn:

Manylion Llyfryddiaeth
Prif Awdur:	Amaru, Luca Gaetano
Fformat:	Llyfr
Iaith:	English
Cyhoeddwyd:	Springer International Publishing 2020
Pynciau:	Engineering Circuits and Systems Processor Architectures Logic Design
Mynediad Ar-lein:	https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85724
Tagiau:	Ychwanegu Tag Dim Tagiau, Byddwch y cyntaf i dagio'r cofnod hwn!

Thư viện lưu trữ:	Thư viện Trường Đại học Đà Lạt

Eitemau Tebyg

ASIC/SoC Functional Design Verification. 1st ed. 2018
gan: Mehta, Ashok B.
Cyhoeddwyd: (2020)

Introduction to Logic Circuits & Logic Design with VHDL
gan: LaMeres, Brock J.
Cyhoeddwyd: (2020)

Introduction to Logic Circuits & Logic Design with Verilog
gan: LaMeres, Brock J.
Cyhoeddwyd: (2020)

High-Level Synthesis
gan: Coussy, Philippe, et al.
Cyhoeddwyd: (2020)

Introduction to Logic Circuits & Logic Design with VHDL . 2nd ed.
gan: LaMeres, Brock J.
Cyhoeddwyd: (2020)

Introduction to Logic Circuits & Logic Design with Verilog. 2nd ed.
gan: LaMeres, Brock J.
Cyhoeddwyd: (2020)

From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators
gan: Rahimi, Abbas, et al.
Cyhoeddwyd: (2020)

Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers
gan: Przigoda, Nils, et al.
Cyhoeddwyd: (2020)

Design of FPGA-Based Computing Systems with OpenCL. 1st ed. 2018
gan: Waidyasooriya, Hasitha Muthumala, et al.
Cyhoeddwyd: (2020)

Testing of Interposer-Based 2.5D Integrated Circuits
gan: Wang, Ran, et al.
Cyhoeddwyd: (2020)

Quick Start Guide to Verilog. 1st ed.
gan: LaMeres, Brock J.
Cyhoeddwyd: (2020)

Fundamentals of Electronic Systems Design
gan: Lienig, Jens, et al.
Cyhoeddwyd: (2020)

Quick Start Guide to VHDL. 1st ed.
gan: LaMeres, Brock J.
Cyhoeddwyd: (2020)

Formal Verification of Simulink/Stateflow Diagrams
gan: Zhan, Naijun, et al.
Cyhoeddwyd: (2020)

Low-Power Design and Power-Aware Verification. 1st ed. 2018
gan: Khondkar, Progyna
Cyhoeddwyd: (2020)

Embedded Software Verification and Debugging
gan: Lettnin, Djones, et al.
Cyhoeddwyd: (2020)

Logic synthesis and verification algorithms
gan: Hachtel, Gary D
Cyhoeddwyd: (2006)

Data-Driven Modeling of Cyber-Physical Systems using Side-Channel Analysis
gan: Chhetri, Sujit Rokka, et al.
Cyhoeddwyd: (2020)

Advanced Logic Synthesis. 1st ed. 2018
gan: Reis, André Inácio, et al.
Cyhoeddwyd: (2020)

Formal System Verification. 1st ed. 2018
gan: Drechsler, Rolf
Cyhoeddwyd: (2020)

Electromigration Inside Logic Cells
gan: Posser, Gracieli, et al.
Cyhoeddwyd: (2020)

Functional Verification of Programmable Embedded Architectures
gan: Mishra, Prabhat, et al.
Cyhoeddwyd: (2020)

Emerging Technology and Architecture for Big-data Analytics
gan: Chattopadhyay, Anupam, et al.
Cyhoeddwyd: (2020)

Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System
gan: Ahmed, Jameel, et al.
Cyhoeddwyd: (2020)

Separation Logic for High-level Synthesis
gan: Winterstein, Felix
Cyhoeddwyd: (2020)

Circuit and Interconnect Design for RF and High Bit-rate Applications
gan: Veenstra, Hugo, et al.
Cyhoeddwyd: (2020)

Timing Performance of Nanometer Digital Circuits Under Process Variations
gan: Champac, Victor, et al.
Cyhoeddwyd: (2020)

Design Techniques for Mash Continuous-Time Delta-Sigma Modulators
gan: Liu, Qiyuan, et al.
Cyhoeddwyd: (2020)

Reliable and Energy Efficient Streaming Multiprocessor Systems
gan: Das, Anup Kumar, et al.
Cyhoeddwyd: (2020)

Simulation and Optimization of Digital Circuits
gan: Melikyan, Vazgen
Cyhoeddwyd: (2020)

Trusted Digital Circuits
gan: Salmani, Hassan
Cyhoeddwyd: (2020)

Physically Unclonable Functions
gan: Halak, Basel
Cyhoeddwyd: (2020)

Deep In-memory Architectures for Machine Learning
gan: Kang, Mingu, et al.
Cyhoeddwyd: (2020)

Energy Efficient High Performance Processors
gan: Haj-Yahya, Jawad, et al.
Cyhoeddwyd: (2020)

Analog Circuit Design
gan: Steyaert, Michiel, et al.
Cyhoeddwyd: (2020)

Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling
gan: Jain, Saurabh, et al.
Cyhoeddwyd: (2020)

Symbolic Parallelization of Nested Loop Programs
gan: Tanase, Alexandru-Petru, et al.
Cyhoeddwyd: (2020)

Advanced Techniques for Power, Energy, and Thermal Management for Clustered Manycores
gan: Pagani, Santiago, et al.
Cyhoeddwyd: (2020)

High-Level Modeling and Synthesis of Analog Integrated Systems
gan: Martens, Ewout S. J., et al.
Cyhoeddwyd: (2020)

Optimized ASIP Synthesis from Architecture Description Language Models
gan: Schliebusch, Oliver, et al.
Cyhoeddwyd: (2020)