New Data Structures and Algorithms for Logic Synthesis and Verification
Đã lưu trong:
Hovedforfatter: | Amaru, Luca Gaetano |
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Format: | Bog |
Sprog: | English |
Udgivet: |
Springer International Publishing
2020
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Fag: | |
Online adgang: | https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85724 |
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Thư viện lưu trữ: | Thư viện Trường Đại học Đà Lạt |
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Lignende værker
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ASIC/SoC Functional Design Verification. 1st ed. 2018
af: Mehta, Ashok B.
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Introduction to Logic Circuits & Logic Design with VHDL
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Introduction to Logic Circuits & Logic Design with Verilog
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High-Level Synthesis
af: Coussy, Philippe, et al.
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Introduction to Logic Circuits & Logic Design with VHDL . 2nd ed.
af: LaMeres, Brock J.
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