New Data Structures and Algorithms for Logic Synthesis and Verification
Gorde:
Egile nagusia: | Amaru, Luca Gaetano |
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Formatua: | Liburua |
Hizkuntza: | English |
Argitaratua: |
Springer International Publishing
2020
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Gaiak: | |
Sarrera elektronikoa: | https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85724 |
Etiketak: |
Etiketa erantsi
Etiketarik gabe, Izan zaitez lehena erregistro honi etiketa jartzen!
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Thư viện lưu trữ: | Thư viện Trường Đại học Đà Lạt |
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Antzeko izenburuak
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ASIC/SoC Functional Design Verification. 1st ed. 2018
nork: Mehta, Ashok B.
Argitaratua: (2020) -
Introduction to Logic Circuits & Logic Design with VHDL
nork: LaMeres, Brock J.
Argitaratua: (2020) -
Introduction to Logic Circuits & Logic Design with Verilog
nork: LaMeres, Brock J.
Argitaratua: (2020) -
High-Level Synthesis
nork: Coussy, Philippe, et al.
Argitaratua: (2020) -
Introduction to Logic Circuits & Logic Design with VHDL . 2nd ed.
nork: LaMeres, Brock J.
Argitaratua: (2020)