Formal Verification of Simulink/Stateflow Diagrams
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| Những tác giả chính: | , , |
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| Định dạng: | Sách |
| Ngôn ngữ: | English |
| Được phát hành: |
Springer International Publishing
2020
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| Những chủ đề: | |
| Truy cập trực tuyến: | http://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85873 |
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| Thư viện lưu trữ: | Thư viện Trường Đại học Đà Lạt |
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oai:scholar.dlu.edu.vn:DLU123456789-85873 |
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oai:scholar.dlu.edu.vn:DLU123456789-858732020-02-24T11:02:32Z Formal Verification of Simulink/Stateflow Diagrams Zhan, Naijun Wang, Shuling Zhao, Hengjun Engineering Circuits and Systems Processor Architectures Electronic Circuits and Devices 2020-02-24T11:02:32Z 2020-02-24T11:02:32Z 2017 Book 978-3-319-47014-6 978-3-319-47016-0 http://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85873 en Springer International Publishing AG application/pdf Springer International Publishing |
| institution |
Thư viện Trường Đại học Đà Lạt |
| collection |
Thư viện số |
| language |
English |
| topic |
Engineering Circuits and Systems Processor Architectures Electronic Circuits and Devices |
| spellingShingle |
Engineering Circuits and Systems Processor Architectures Electronic Circuits and Devices Zhan, Naijun Wang, Shuling Zhao, Hengjun Formal Verification of Simulink/Stateflow Diagrams |
| format |
Book |
| author |
Zhan, Naijun Wang, Shuling Zhao, Hengjun |
| author_facet |
Zhan, Naijun Wang, Shuling Zhao, Hengjun |
| author_sort |
Zhan, Naijun |
| title |
Formal Verification of Simulink/Stateflow Diagrams |
| title_short |
Formal Verification of Simulink/Stateflow Diagrams |
| title_full |
Formal Verification of Simulink/Stateflow Diagrams |
| title_fullStr |
Formal Verification of Simulink/Stateflow Diagrams |
| title_full_unstemmed |
Formal Verification of Simulink/Stateflow Diagrams |
| title_sort |
formal verification of simulink/stateflow diagrams |
| publisher |
Springer International Publishing |
| publishDate |
2020 |
| url |
http://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85873 |
| _version_ |
1757669456360767488 |