Formal Verification of Simulink/Stateflow Diagrams

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Formal Verification of Simulink/Stateflow Diagrams

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Dades bibliogràfiques
Autors principals:	Zhan, Naijun, Wang, Shuling, Zhao, Hengjun
Format:	Llibre
Idioma:	English
Publicat:	Springer International Publishing 2020
Matèries:	Engineering Circuits and Systems Processor Architectures Electronic Circuits and Devices
Accés en línia:	https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85873
Etiquetes:	Afegir etiqueta Sense etiquetes, Sigues el primer a etiquetar aquest registre!

Thư viện lưu trữ:	Thư viện Trường Đại học Đà Lạt

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