Formal Verification of Simulink/Stateflow Diagrams

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Formal Verification of Simulink/Stateflow Diagrams

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Xehetasun bibliografikoak
Egile Nagusiak:	Zhan, Naijun, Wang, Shuling, Zhao, Hengjun
Formatua:	Liburua
Hizkuntza:	English
Argitaratua:	Springer International Publishing 2020
Gaiak:	Engineering Circuits and Systems Processor Architectures Electronic Circuits and Devices
Sarrera elektronikoa:	https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85873
Etiketak:	Etiketa erantsi Etiketarik gabe, Izan zaitez lehena erregistro honi etiketa jartzen!

Thư viện lưu trữ:	Thư viện Trường Đại học Đà Lạt

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