Formal Verification of Simulink/Stateflow Diagrams
Enregistré dans:
Auteurs principaux: | Zhan, Naijun, Wang, Shuling, Zhao, Hengjun |
---|---|
Format: | Livre |
Langue: | English |
Publié: |
Springer International Publishing
2020
|
Sujets: | |
Accès en ligne: | https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85873 |
Tags: |
Ajouter un tag
Pas de tags, Soyez le premier à ajouter un tag!
|
Thư viện lưu trữ: | Thư viện Trường Đại học Đà Lạt |
---|
Documents similaires
-
Formal System Verification. 1st ed. 2018
par: Drechsler, Rolf
Publié: (2020) -
Invasive Computing for Mapping Parallel Programs to Many-Core Architectures. 1st ed. 2018
par: Weichslgartner, Andreas, et autres
Publié: (2020) -
Energy-Efficient Smart Temperature Sensors in CMOS Technology. 1st ed. 2018
par: Souri, Kamran, et autres
Publié: (2020) -
Neuro-inspired Computing Using Resistive Synaptic Devices
par: Yu, Shimeng
Publié: (2020) -
Circadian Rhythms for Future Resilient Electronic Systems
par: Guo, Xinfei, et autres
Publié: (2020)