Formal Verification of Simulink/Stateflow Diagrams

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Formal Verification of Simulink/Stateflow Diagrams

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書誌詳細
主要な著者:	Zhan, Naijun, Wang, Shuling, Zhao, Hengjun
フォーマット:	図書
言語:	English
出版事項:	Springer International Publishing 2020
主題:	Engineering Circuits and Systems Processor Architectures Electronic Circuits and Devices
オンライン･アクセス:	https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85873
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Thư viện lưu trữ:	Thư viện Trường Đại học Đà Lạt

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