Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard

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Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard

IEEE Access, Vol 12; pp: 32395-32407.

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Dades bibliogràfiques
Autors principals:	Truong, Quang Dang, Duong, Ngoc Phap, Lee, Hanho
Format:	Bài viết
Idioma:	Vietnamese
Publicat:	IEEE 2024
Matèries:	Post-quantum cryptography (PQC) module-lattice-based digital signature standard (ML-DSA) crystals-Dilithium lattice-based cryptography (LBC) number theoretic transform (NTT)
Accés en línia:	https://elib.vku.udn.vn/handle/123456789/4013
Etiquetes:	Afegir etiqueta Sense etiquetes, Sigues el primer a etiquetar aquest registre!

Thư viện lưu trữ:	Trường Đại học Công nghệ Thông tin và Truyền thông Việt Hàn - Đại học Đà Nẵng

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