Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects

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Những tác giả chính:	Lourenço, Nuno, Martins, Ricardo, Horta, Nuno
Định dạng:	Sách
Ngôn ngữ:	English
Được phát hành:	Springer International Publishing 2020
Những chủ đề:	Engineering Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation
Truy cập trực tuyến:	http://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85690
Các nhãn:	Thêm thẻ Không có thẻ, Là người đầu tiên thẻ bản ghi này!

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id	oai:scholar.dlu.edu.vn:DLU123456789-85690
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spelling	oai:scholar.dlu.edu.vn:DLU123456789-856902020-02-24T10:54:50Z Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects Lourenço, Nuno Martins, Ricardo Horta, Nuno Engineering Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation 2020-02-24T10:54:50Z 2020-02-24T10:54:50Z 2017 Book 978-3-319-42036-3 978-3-319-42037-0 http://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85690 en Springer International Publishing Switzerland application/pdf Springer International Publishing
institution	Thư viện Trường Đại học Đà Lạt
collection	Thư viện số
language	English
topic	Engineering Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation
spellingShingle	Engineering Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation Lourenço, Nuno Martins, Ricardo Horta, Nuno Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
format	Book
author	Lourenço, Nuno Martins, Ricardo Horta, Nuno
author_facet	Lourenço, Nuno Martins, Ricardo Horta, Nuno
author_sort	Lourenço, Nuno
title	Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
title_short	Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
title_full	Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
title_fullStr	Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
title_full_unstemmed	Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
title_sort	automatic analog ic sizing and optimization constrained with pvt corners and layout effects
publisher	Springer International Publishing
publishDate	2020
url	http://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85690
_version_	1757673832805564416

Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects

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