New Data Structures and Algorithms for Logic Synthesis and Verification
Enregistré dans:
Auteur principal: | Amaru, Luca Gaetano |
---|---|
Format: | Livre |
Langue: | English |
Publié: |
Springer International Publishing
2020
|
Sujets: | |
Accès en ligne: | https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85724 |
Tags: |
Ajouter un tag
Pas de tags, Soyez le premier à ajouter un tag!
|
Thư viện lưu trữ: | Thư viện Trường Đại học Đà Lạt |
---|
Documents similaires
-
ASIC/SoC Functional Design Verification. 1st ed. 2018
par: Mehta, Ashok B.
Publié: (2020) -
Introduction to Logic Circuits & Logic Design with VHDL
par: LaMeres, Brock J.
Publié: (2020) -
Introduction to Logic Circuits & Logic Design with Verilog
par: LaMeres, Brock J.
Publié: (2020) -
High-Level Synthesis
par: Coussy, Philippe, et autres
Publié: (2020) -
Introduction to Logic Circuits & Logic Design with VHDL . 2nd ed.
par: LaMeres, Brock J.
Publié: (2020)