Formal Verification of Simulink/Stateflow Diagrams

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Formal Verification of Simulink/Stateflow Diagrams

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Sonraí Bibleagrafaíochta
Những tác giả chính:	Zhan, Naijun, Wang, Shuling, Zhao, Hengjun
Formáid:	Leabhar
Teanga:	English
Foilsithe:	Springer International Publishing 2020
Ábhair:	Engineering Circuits and Systems Processor Architectures Electronic Circuits and Devices
Rochtain Ar Líne:	https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85873
Clibeanna:	Cuir Clib Leis Gan Chlibeanna, Bí ar an gcéad duine leis an taifead seo a chlibeáil!

Thư viện lưu trữ:	Thư viện Trường Đại học Đà Lạt

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