Formal Verification of Simulink/Stateflow Diagrams

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Formal Verification of Simulink/Stateflow Diagrams

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Opis bibliograficzny
Główni autorzy:	Zhan, Naijun, Wang, Shuling, Zhao, Hengjun
Format:	Książka
Język:	English
Wydane:	Springer International Publishing 2020
Hasła przedmiotowe:	Engineering Circuits and Systems Processor Architectures Electronic Circuits and Devices
Dostęp online:	https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/85873
Etykiety:	Dodaj etykietę Nie ma etykietki, Dołącz pierwszą etykiete!

Thư viện lưu trữ:	Thư viện Trường Đại học Đà Lạt

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