Applied formal verification
Formal verification is a powerful new digital design method. In this cutting-edge tutorial, two of the field's best known authors team up to show designers how to efficiently apply Formal Verification, along with hardware description languages like Verilog and VHDL, to more efficiently solve re...
Đã lưu trong:
| 主要作者: | |
|---|---|
| 格式: | 图书 |
| 语言: | Undetermined |
| 出版: |
New York
McGraw-Hill
2005
|
| 主题: | |
| 标签: |
添加标签
没有标签, 成为第一个标记此记录!
|
| Thư viện lưu trữ: | Trung tâm Học liệu Trường Đại học Cần Thơ |
|---|
成为第一个发表评论!