Nanoscale CMOS VLSI Circuits: Design for Manufacturability /
Cutting-Edge CMOS VLSI Design for Manufacturability Techniques
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| Tác giả chính: | |
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| Tác giả khác: | |
| Định dạng: | Sách |
| Ngôn ngữ: | Vietnamese |
| Được phát hành: |
NewYork :
Mc Graw-Hill ,
2010
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| Những chủ đề: | |
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| Thư viện lưu trữ: | Thư viện Trường CĐ Kỹ Thuật Cao Thắng |
|---|
| LEADER | 01697nam a2200289 a 4500 | ||
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| 005 | 20140617000000 | ||
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| 980 | \ | \ | |a Thư viện Trường CĐ Kỹ Thuật Cao Thắng |
| 024 | |a RG_1 #1 eb0 i1 | ||
| 020 | # | # | |a 007163519X |
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| 082 | # | # | |a 621.395 / |b N100N-s |
| 100 | 1 | # | |a Kundu Sandip |
| 245 | 0 | 0 | |a Nanoscale CMOS VLSI Circuits: Design for Manufacturability / |c Kundu Sandip, Sreedhar Aswin |
| 260 | # | # | |a NewYork : |b Mc Graw-Hill , |c 2010 |
| 300 | # | # | |a 316tr. |
| 520 | # | # | |a Cutting-Edge CMOS VLSI Design for Manufacturability Techniques |
| 520 | # | # | |a This detailed guide offers proven methods for optimizing circuit designs to increase the yield, reliability, and manufacturability of products and mitigate defects and failure. Covering the latest devices, technologies, and processes, Nanoscale CMOS VLSI Circuits: Design for Manufacturability focuses on delivering higher performance and lower power consumption. Costs, constraints, and computational efficiencies are also discussed in the practical resource. |
| 520 | # | # | |a Nanoscale CMOS VLSI Circuits covers: |
| 520 | # | # | |a Current trends in CMOS VLSI design |
| 520 | # | # | |a Dr. Sandip Kundu is a professor in the Electrical and Computer Engineering Department at the University of Massachusetts at Amherst, specializing in semiconductor and lithographic manufacturing. |
| 520 | # | # | |a Dr. Aswin Sreedhar is a research assistant at the Electrical and Computer Engineering Department at the University of Massachusetts. |
| 650 | # | 4 | |a Nanoscale |
| 650 | # | 4 | |a CMOS VLSI Circuits |
| 700 | 0 | # | |a Sreedhar Aswin |