High Performance VLSI Architectures for QC-LDPC Codes in 5G Communications
Chapter1. Introduction; Chapter 2. Background and Fundamentals; Chapter 3. Low-Complexity Multi-Way Split-Row Layered LDPC Decoder for Gigabit Wireless Communications; ...
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| Idioma: | eng |
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Inha University
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https:--dlib.udn.vn-module-chi-tiet-sach?RecordID=28922025-04-21T00:00:00ZNguyen Thi Bao TramHigh Performance VLSI Architectures for QC-LDPC Codes in 5G CommunicationsKiến trúc VLSI hiệu suất cao cho bộ mã QC-LDPC trong hệ thống thông tin 5GInha UniversityChapter1. Introduction; Chapter 2. Background and Fundamentals; Chapter 3. Low-Complexity Multi-Way Split-Row Layered LDPC Decoder for Gigabit Wireless Communications; ...engInha Universityhttps://dlib.udn.vn/module/chi-tiet-sach?RecordID=2892 |
| institution |
Trung tâm Công nghệ thông tin và Học liệu số, Đại học Đà Nẵng |
| collection |
DSpace |
| language |
eng |
| description |
Chapter1. Introduction; Chapter 2. Background and Fundamentals; Chapter 3. Low-Complexity Multi-Way Split-Row Layered LDPC Decoder for Gigabit Wireless Communications; ... |
| author |
Nguyen Thi Bao Tram |
| spellingShingle |
Nguyen Thi Bao Tram High Performance VLSI Architectures for QC-LDPC Codes in 5G Communications |
| author_facet |
Nguyen Thi Bao Tram |
| author_sort |
Nguyen Thi Bao Tram |
| title |
High Performance VLSI Architectures for QC-LDPC Codes in 5G Communications |
| title_short |
High Performance VLSI Architectures for QC-LDPC Codes in 5G Communications |
| title_full |
High Performance VLSI Architectures for QC-LDPC Codes in 5G Communications |
| title_fullStr |
High Performance VLSI Architectures for QC-LDPC Codes in 5G Communications |
| title_full_unstemmed |
High Performance VLSI Architectures for QC-LDPC Codes in 5G Communications |
| title_sort |
high performance vlsi architectures for qc-ldpc codes in 5g communications |
| publisher |
Inha University |
| url |
https://dlib.udn.vn/module/chi-tiet-sach?RecordID=2892 |
| _version_ |
1848657518949040128 |