High Performance VLSI Architectures for QC-LDPC Codes in 5G Communications
Chapter1. Introduction; Chapter 2. Background and Fundamentals; Chapter 3. Low-Complexity Multi-Way Split-Row Layered LDPC Decoder for Gigabit Wireless Communications; ...
Gorde:
| Egile nagusia: | Nguyen Thi Bao Tram |
|---|---|
| Hizkuntza: | eng |
| Argitaratua: |
Inha University
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| Sarrera elektronikoa: | https://dlib.udn.vn/module/chi-tiet-sach?RecordID=2892 |
| Etiketak: |
Etiketa erantsi
Etiketarik gabe, Izan zaitez lehena erregistro honi etiketa jartzen!
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| Thư viện lưu trữ: | Trung tâm Công nghệ thông tin và Học liệu số, Đại học Đà Nẵng |
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Antzeko izenburuak
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LDPC Coded Modulations
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VLSI test principles and architectures :
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Argitaratua: (2020) -
High Performance Embedded Architectures and Compilers
nork: Bosschere, Koen De, et al.
Argitaratua: (2020) -
High Performance Embedded Architectures and Compilers
Argitaratua: (2020)