A VERY LOW BANDGAP LINE-TUNNEL FIELD EFFECT TRANSISTOR WITH CHANNEL-BURIED OXIDE AND LATERALLY DOPED POCKET
Low bandgap and line tunneling techniques have demonstrated the most effectiveness in enhancing the on-current of tunnel field-effect transistors (TFETs). This study examines the mechanisms and designs of channel-buried oxide and a laterally doped pocket for a very low bandgap line-TFET. Numerical T...
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| Những tác giả chính: | , , |
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| 格式: | Bài viết |
| 语言: | English |
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Trường Đại học Đà Lạt
2024
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| 在线阅读: | https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/256919 https://tckh.dlu.edu.vn/index.php/tckhdhdl/article/view/1313 |
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| Thư viện lưu trữ: | Thư viện Trường Đại học Đà Lạt |
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| 总结: | Low bandgap and line tunneling techniques have demonstrated the most effectiveness in enhancing the on-current of tunnel field-effect transistors (TFETs). This study examines the mechanisms and designs of channel-buried oxide and a laterally doped pocket for a very low bandgap line-TFET. Numerical TCAD simulations show that the channel-buried oxide is needed to prevent off-state lateral tunneling while still maintaining the on-state vertical tunneling. The buried oxide pillar should be high so that the channel is thin, about 10 nm thick, to completely suppress the tunneling leakage. The dopant pocket is required to trigger the line tunneling earlier than the point tunneling to improve the subthreshold swing and on-current. Increasing the pocket concentration or decreasing the pocket thickness both cause an increase not only in the vertical band bending but also in the effective gate-insulator thickness. Because of the trade-off between these two operation parameters, for a given thickness/concentration, there exists an optimal concentration/thickness of the pocket to maximize the on-current. The on-current is optimized using a heavy, thin pocket, for which the band bending is maximized and the effective gate-insulator thickness is minimized. For the fabrication feasibility using existing doping techniques, the pocket concentration and thickness should be 1019 cm-3 and 4 nm, respectively, to maximize the on-current of the InAs line-TFET. |
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