Flip-Flop Design in Nanometer CMOS (From High Speed to Low Energy)
The design of the clocking subsystem represents a crucial aspect in CMOS VLSI integrated circuits, as it strongly affects not only the chip performance, but also its overall energy consumption. Independently of the nature of the system (fully synchronous, globally asynchronous, locally synchronou...
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| Những tác giả chính: | , , |
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| Định dạng: | Sách |
| Ngôn ngữ: | English |
| Được phát hành: |
Springer
2015
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| Những chủ đề: | |
| Truy cập trực tuyến: | https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/56114 |
| Các nhãn: |
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| Thư viện lưu trữ: | Thư viện Trường Đại học Đà Lạt |
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| Tóm tắt: | The design of the clocking subsystem represents a crucial aspect in CMOS VLSI
integrated circuits, as it strongly affects not only the chip performance, but also its
overall energy consumption. Independently of the nature of the system (fully
synchronous, globally asynchronous, locally synchronous), any clocking subsystem
can be subdivided into three main parts: similar to the structure of a tree, the
root is represented by the clock generation, the branches are represented by the
circuits devoted to clock distribution, and the clocked storage elements (i.e., latches
and/or flip-flops) are the final leaves. Flip-flops (or, more in general, clocked
storage elements) are among the most important cells used in digital systems, such
as microprocessors. They separate the various stages that pipelines are made up of,
hold the state, and prevent early transitions that would be otherwise determined by
fast paths. Overall, flip-flops synchronize and regulate the entire flow of data
within a digital system... |
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