Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor Applications
Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog techn...
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2015
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oai:scholar.dlu.edu.vn:DLU123456789-591322023-11-11T06:31:07Z Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor Applications Qu, Shichun Liu, Yong Chip scale packaging Mechanical Electronics Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Since the analog and power electronic wafer level packaging is different from regular digital and memory IC package, this book will systematically introduce the typical analog and power electronic wafer level packaging design, assembly process, materials, reliability and failure analysis, and material selection. 2015-11-05T02:36:35Z 2015-11-05T02:36:35Z 2015 Book 978-1-4939-1556-9 https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/59132 en application/pdf Springer |
| institution |
Thư viện Trường Đại học Đà Lạt |
| collection |
Thư viện số |
| language |
English |
| topic |
Chip scale packaging Mechanical Electronics |
| spellingShingle |
Chip scale packaging Mechanical Electronics Qu, Shichun Liu, Yong Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor Applications |
| description |
Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Since the analog and power electronic wafer level packaging is different from regular digital and memory IC package, this book will systematically introduce the typical analog and power electronic wafer level packaging design, assembly process, materials, reliability and failure analysis, and material selection. |
| format |
Book |
| author |
Qu, Shichun Liu, Yong |
| author_facet |
Qu, Shichun Liu, Yong |
| author_sort |
Qu, Shichun |
| title |
Wafer-Level Chip-Scale Packaging
Analog and Power Semiconductor Applications |
| title_short |
Wafer-Level Chip-Scale Packaging
Analog and Power Semiconductor Applications |
| title_full |
Wafer-Level Chip-Scale Packaging
Analog and Power Semiconductor Applications |
| title_fullStr |
Wafer-Level Chip-Scale Packaging
Analog and Power Semiconductor Applications |
| title_full_unstemmed |
Wafer-Level Chip-Scale Packaging
Analog and Power Semiconductor Applications |
| title_sort |
wafer-level chip-scale packaging
analog and power semiconductor applications |
| publisher |
Springer |
| publishDate |
2015 |
| url |
https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/59132 |
| _version_ |
1819768544691224576 |