Phase-locked loop synthesizer simulation
Phase locked loops (PLLs) are electronic circuits that ensure that a communications signal stays locked on a given frequency. Their design is crucial to the workings of wireless communications systems. Virtually all transceivers use PLLs to synthesize the stable, high frequency oscillations necessar...
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| 第一著者: | |
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| フォーマット: | 図書 |
| 言語: | Undetermined |
| 出版事項: |
New York
McGraw-Hill
2005
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| Thư viện lưu trữ: | Trung tâm Học liệu Trường Đại học Cần Thơ |
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| 要約: | Phase locked loops (PLLs) are electronic circuits that ensure that a communications signal stays locked on a given frequency. Their design is crucial to the workings of wireless communications systems. Virtually all transceivers use PLLs to synthesize the stable, high frequency oscillations necessary for radio & wireless. This book describes how to calculate PLL performances by using standard mathematical or circuit analysis programs. Theoretical descriptions are limited to the minimum needed to explain how to perform calculations. Although presented methods of analysis can be implemented with many commercial programs, their description always refers to Mathcad and SIMetrix. |
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