Phase-locked loop synthesizer simulation
Phase locked loops (PLLs) are electronic circuits that ensure that a communications signal stays locked on a given frequency. Their design is crucial to the workings of wireless communications systems. Virtually all transceivers use PLLs to synthesize the stable, high frequency oscillations necessar...
Tallennettuna:
Päätekijä: | Bianchi, Giovanni |
---|---|
Aineistotyyppi: | Kirja |
Kieli: | Undetermined |
Julkaistu: |
New York
McGraw-Hill
2005
|
Aiheet: | |
Tagit: |
Lisää tagi
Ei tageja, Lisää ensimmäinen tagi!
|
Thư viện lưu trữ: | Trung tâm Học liệu Trường Đại học Cần Thơ |
---|
Samankaltaisia teoksia
-
Phase-locked loop synthesizer simulation /
Tekijä: Bianchi, Giovanni.
Julkaistu: (2005) -
Phase-locked loop synthesizer simulation
Tekijä: Bianchi, Giovanni
Julkaistu: (2005) -
A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel
Tekijä: Purkayastha, Basab Bijoy, et al.
Julkaistu: (2015) -
Phase-locked loop synthesizer simulation
Tekijä: Bianchi, Giovanni.
Julkaistu: (2005) -
Catalytic enantioselective strecker reactions and analogous syntheses /
Tekijä: Groger, Harald.