Phase-locked loop synthesizer simulation
Phase locked loops (PLLs) are electronic circuits that ensure that a communications signal stays locked on a given frequency. Their design is crucial to the workings of wireless communications systems. Virtually all transceivers use PLLs to synthesize the stable, high frequency oscillations necessar...
में बचाया:
मुख्य लेखक: | Bianchi, Giovanni |
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स्वरूप: | पुस्तक |
भाषा: | Undetermined |
प्रकाशित: |
New York
McGraw-Hill
2005
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विषय: | |
टैग : |
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Thư viện lưu trữ: | Trung tâm Học liệu Trường Đại học Cần Thơ |
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समान संसाधन
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Phase-locked loop synthesizer simulation /
द्वारा: Bianchi, Giovanni.
प्रकाशित: (2005) -
Phase-locked loop synthesizer simulation
द्वारा: Bianchi, Giovanni
प्रकाशित: (2005) -
A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel
द्वारा: Purkayastha, Basab Bijoy, और अन्य
प्रकाशित: (2015) -
Phase-locked loop synthesizer simulation
द्वारा: Bianchi, Giovanni.
प्रकाशित: (2005) -
Catalytic enantioselective strecker reactions and analogous syntheses /
द्वारा: Groger, Harald.