Phase-locked loop synthesizer simulation
Phase locked loops (PLLs) are electronic circuits that ensure that a communications signal stays locked on a given frequency. Their design is crucial to the workings of wireless communications systems. Virtually all transceivers use PLLs to synthesize the stable, high frequency oscillations necessar...
Sparad:
Huvudupphovsman: | Bianchi, Giovanni |
---|---|
Materialtyp: | Bok |
Språk: | Undetermined |
Publicerad: |
New York
McGraw-Hill
2005
|
Ämnen: | |
Taggar: |
Lägg till en tagg
Inga taggar, Lägg till första taggen!
|
Thư viện lưu trữ: | Trung tâm Học liệu Trường Đại học Cần Thơ |
---|
Liknande verk
-
Phase-locked loop synthesizer simulation /
av: Bianchi, Giovanni.
Publicerad: (2005) -
Phase-locked loop synthesizer simulation
av: Bianchi, Giovanni
Publicerad: (2005) -
A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel
av: Purkayastha, Basab Bijoy, et al.
Publicerad: (2015) -
Phase-locked loop synthesizer simulation
av: Bianchi, Giovanni.
Publicerad: (2005) -
Catalytic enantioselective strecker reactions and analogous syntheses /
av: Groger, Harald.