Logic synthesis and verification algorithms

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Logic synthesis and verification algorithms

Includes bibliographical references and index

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Podrobná bibliografie
Hlavní autor:	Hachtel, Gary D
Další autoři:	Somenzi, Fabio
Médium:	Kniha
Jazyk:	Undetermined
Vydáno:	New York Springer 2006
Témata:	Integrated circuits > Very large scale integration > Design > Data processing; Logic design > Data processing; Mạch tích hợp > Thiết kế > Xử lý dữ liệu; Thiết kế logic > Xử lý dữ liệu
On-line přístup:	http://lrc.tdmu.edu.vn/opac/search/detail.asp?aID=2&ID=35611
Tagy:	Přidat tag Žádné tagy, Buďte první, kdo otaguje tento záznam!

Thư viện lưu trữ:	Trung tâm Học liệu Trường Đại học Thủ Dầu Một


LEADER	00888nam a2200217Ia 4500
001	TDMU_35611
008	210410s9999 xx 000 0 und d
082			\|a 330.9
090			\|b H102
100			\|a Hachtel, Gary D
245		0	\|a Logic synthesis and verification algorithms
245		0	\|c Gary Hachtel, Fabio Somenzi
260			\|a New York
260			\|b Springer
260			\|c 2006
300			\|a xxxii, 564 p.
520			\|a Includes bibliographical references and index
650			\|a Integrated circuits \|x Very large scale integration \|x Design \|x Data processing; Logic design \|x Data processing; Mạch tích hợp \|x Thiết kế \|x Xử lý dữ liệu; Thiết kế logic \|x Xử lý dữ liệu
700			\|a Somenzi, Fabio
856			\|u http://lrc.tdmu.edu.vn/opac/search/detail.asp?aID=2&ID=35611
980			\|a Trung tâm Học liệu Trường Đại học Thủ Dầu Một