High Performance VLSI Architectures for QC-LDPC Codes in 5G Communications
Chapter1. Introduction; Chapter 2. Background and Fundamentals; Chapter 3. Low-Complexity Multi-Way Split-Row Layered LDPC Decoder for Gigabit Wireless Communications; ...
Zapisane w:
| 1. autor: | Nguyen Thi Bao Tram |
|---|---|
| Język: | eng |
| Wydane: |
Inha University
|
| Dostęp online: | https://dlib.udn.vn/module/chi-tiet-sach?RecordID=2892 |
| Etykiety: |
Dodaj etykietę
Nie ma etykietki, Dołącz pierwszą etykiete!
|
| Thư viện lưu trữ: | Trung tâm Công nghệ thông tin và Học liệu số, Đại học Đà Nẵng |
|---|
Podobne zapisy
-
LDPC Coded Modulations
od: Franceschini, Michele, i wsp.
Wydane: (2020) -
VLSI test principles and architectures :
Wydane: (2006) -
High-performance Packet Switching Architectures
od: Elhanany, Itamar, i wsp.
Wydane: (2020) -
High Performance Embedded Architectures and Compilers
od: Bosschere, Koen De, i wsp.
Wydane: (2020) -
High Performance Embedded Architectures and Compilers
Wydane: (2020)