High Performance VLSI Architectures for QC-LDPC Codes in 5G Communications
Chapter1. Introduction; Chapter 2. Background and Fundamentals; Chapter 3. Low-Complexity Multi-Way Split-Row Layered LDPC Decoder for Gigabit Wireless Communications; ...
Shranjeno v:
| Glavni avtor: | Nguyen Thi Bao Tram |
|---|---|
| Jezik: | eng |
| Izdano: |
Inha University
|
| Online dostop: | https://dlib.udn.vn/module/chi-tiet-sach?RecordID=2892 |
| Oznake: |
Označite
Brez oznak, prvi označite!
|
| Thư viện lưu trữ: | Trung tâm Công nghệ thông tin và Học liệu số, Đại học Đà Nẵng |
|---|
Podobne knjige/članki
-
LDPC Coded Modulations
od: Franceschini, Michele, et al.
Izdano: (2020) -
VLSI test principles and architectures :
Izdano: (2006) -
High-performance Packet Switching Architectures
od: Elhanany, Itamar, et al.
Izdano: (2020) -
High Performance Embedded Architectures and Compilers
od: Bosschere, Koen De, et al.
Izdano: (2020) -
High Performance Embedded Architectures and Compilers
Izdano: (2020)