Applied formal verification

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Applied formal verification

Formal verification is a powerful new digital design method. In this cutting-edge tutorial, two of the field's best known authors team up to show designers how to efficiently apply Formal Verification, along with hardware description languages like Verilog and VHDL, to more efficiently solve re...

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Dades bibliogràfiques
Autor principal:	Perry, Douglas L.
Format:	Llibre
Idioma:	Undetermined
Publicat:	New York McGraw-Hill 2005
Matèries:	Integrated circuits,Electronic circuits Verification,Testing
Etiquetes:	Afegir etiqueta Sense etiquetes, Sigues el primer a etiquetar aquest registre!

Thư viện lưu trữ:	Trung tâm Học liệu Trường Đại học Cần Thơ

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