Applied formal verification

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Applied formal verification

Formal verification is a powerful new digital design method. In this cutting-edge tutorial, two of the field's best known authors team up to show designers how to efficiently apply Formal Verification, along with hardware description languages like Verilog and VHDL, to more efficiently solve re...

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書目詳細資料
主要作者:	Perry, Douglas L.
格式:	圖書
語言:	Undetermined
出版:	New York McGraw-Hill 2005
主題:	Integrated circuits,Electronic circuits Verification,Testing
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

Thư viện lưu trữ:	Trung tâm Học liệu Trường Đại học Cần Thơ

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