Verification techniques for system-level design
This book will explain how to verify SoC logic designs using "formal" and "semi-formal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correct...
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| Formaat: | Boek |
| Taal: | Undetermined |
| Gepubliceerd in: |
Amsterdam
Morgan Kaufmann Publishers
2008
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| Onderwerpen: | |
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| Thư viện lưu trữ: | Trung tâm Học liệu Trường Đại học Cần Thơ |
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| Samenvatting: | This book will explain how to verify SoC logic designs using "formal" and "semi-formal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional" verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. |
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