Verification techniques for system-level design
This book will explain how to verify SoC logic designs using "formal" and "semi-formal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correct...
Guardat en:
| Autor principal: | |
|---|---|
| Format: | Llibre |
| Idioma: | Undetermined |
| Publicat: |
Amsterdam
Morgan Kaufmann Publishers
2008
|
| Matèries: | |
| Etiquetes: |
Afegir etiqueta
Sense etiquetes, Sigues el primer a etiquetar aquest registre!
|
| Thư viện lưu trữ: | Trung tâm Học liệu Trường Đại học Cần Thơ |
|---|
Sigues el primer a deixar un comentari!