SVA: The Power of Assertions in System Verilog
This book is the result of the deep involvement of the authors in the development of EDA tools, SystemVerilog Assertion standardization, and many years of practical experience. One of the goals of this book is to expose the oral knowhow circulated among design and verification engineers which has...
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| Những tác giả chính: | , , , |
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| Định dạng: | Sách |
| Ngôn ngữ: | English |
| Được phát hành: |
Springer
2015
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| Những chủ đề: | |
| Truy cập trực tuyến: | https://scholar.dlu.edu.vn/thuvienso/handle/DLU123456789/56811 |
| Các nhãn: |
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| Thư viện lưu trữ: | Thư viện Trường Đại học Đà Lạt |
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| Tóm tắt: | This book is the result of the deep involvement of the authors in the development of
EDA tools, SystemVerilog Assertion standardization, and many years of practical
experience. One of the goals of this book is to expose the oral knowhow circulated
among design and verification engineers which has never been written down in
its full extent. The book thus contains many practical examples and exercises
illustrating the various concepts and semantics of the SystemVerilog assertion
language. Much attention is given to discussing efficiency of assertion forms in
simulation and formal verification. We did our best to validate all the examples, but
there are hundreds of them and not all features could be validated since they have
not yet been implemented in EDA tools. Therefore, we will be grateful to readers for
pointing to us any needed corrections. The book is written in a way that we believe
serves well both the users of SystemVerilog assertions in simulation and also those
who practice formal verification (model checking). Compared to previous books
covering SystemVerilog assertions we include in detail the most recent features
that appeared in the IEEE 1800–2009 SystemVerilog Standard and were further
improved and enhanced in the recent IEEE 1800–2012 Standard. In particular, it
concerns the new encapsulation construct “checker” and checker libraries, Linear
Temporal Logic operators, and semantics and usage in formal verification. However,
for integral understanding we present the assertion language and its applications in
full detail... |
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