Applied formal verification
Formal verification is a powerful new digital design method. In this cutting-edge tutorial, two of the field's best known authors team up to show designers how to efficiently apply Formal Verification, along with hardware description languages like Verilog and VHDL, to more efficiently solve re...
সংরক্ষণ করুন:
| প্রধান লেখক: | |
|---|---|
| বিন্যাস: | গ্রন্থ |
| ভাষা: | Undetermined |
| প্রকাশিত: |
New York
McGraw-Hill
2005
|
| বিষয়গুলি: | |
| ট্যাগগুলো: |
ট্যাগ যুক্ত করুন
কোনো ট্যাগ নেই, প্রথমজন হিসাবে ট্যাগ করুন!
|
| Thư viện lưu trữ: | Trung tâm Học liệu Trường Đại học Cần Thơ |
|---|