Applied formal verification

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Applied formal verification

Formal verification is a powerful new digital design method. In this cutting-edge tutorial, two of the field's best known authors team up to show designers how to efficiently apply Formal Verification, along with hardware description languages like Verilog and VHDL, to more efficiently solve re...

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书目详细资料
主要作者:	Perry, Douglas L.
格式:	图书
语言:	Undetermined
出版:	New York McGraw-Hill 2005
主题:	Integrated circuits,Electronic circuits Verification,Testing
标签:	添加标签没有标签, 成为第一个标记此记录!

Thư viện lưu trữ:	Trung tâm Học liệu Trường Đại học Cần Thơ

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