Short-channel effect and device design of extremely scaled tunnel field-effect transistors

Short-channel effect and device design of extremely scaled tunnel field-effect transistors

For serving as ideal switching devices in future energy-efficient applications, scaling down the channel lengths of Tunnel-Field Effect Transistors (TFETs) is essential to follow the pace of Si-based CMOS technologies. This work elucidates the short-channel mechanisms and the role of the drain in ex...

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Những tác giả chính: Nguyễn, Đăng Chiến, Chun-Hsing Shih
Định dạng: Journal article
Ngôn ngữ:English
Được phát hành: 2023
Những chủ đề:
Short-Channel Effect
Tunnel Field-Effect Transistor
Device Design
Truy cập trực tuyến:https://scholar.dlu.edu.vn/handle/123456789/2082
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Thư viện lưu trữ: Thư viện Trường Đại học Đà Lạt
id oai:scholar.dlu.edu.vn:123456789-2082
record_format dspace
institution Thư viện Trường Đại học Đà Lạt
collection Thư viện số
language English
topic Short-Channel Effect
Tunnel Field-Effect Transistor
Device Design
spellingShingle Short-Channel Effect
Tunnel Field-Effect Transistor
Device Design
Nguyễn, Đăng Chiến
Chun-Hsing Shih
Short-channel effect and device design of extremely scaled tunnel field-effect transistors
description For serving as ideal switching devices in future energy-efficient applications, scaling down the channel lengths of Tunnel-Field Effect Transistors (TFETs) is essential to follow the pace of Si-based CMOS technologies. This work elucidates the short-channel mechanisms and the role of the drain in extremely-scaled TFETs. The scalability of TFETs depends strongly on the appropriately low drain concentration, whereas the capability of the drain for scaling relies on a sufficient drain region. The drain with a light concentration of 5×1017 cm-3 and a minimum length of 20nm enables 5nm TFETs to exhibit favorable on-off switching characteristics. In sub-20nm TFETs, the total drain and channel lengths must satisfy the minimum criteria of approximately 25nm to sustain reversely biased drain voltage of 0.7V. The asymmetric Si1-xGex source heterojunction is combined with the minimum drain design in 5nm TFETs to separately optimize the source- and drain-side tunnel junctions, generating ideal on-/off-currents and switching characteristics to serve as a promising design approach of sub-5nm TFETs.
format Journal article
author Nguyễn, Đăng Chiến
Chun-Hsing Shih
author_facet Nguyễn, Đăng Chiến
Chun-Hsing Shih
author_sort Nguyễn, Đăng Chiến
title Short-channel effect and device design of extremely scaled tunnel field-effect transistors
title_short Short-channel effect and device design of extremely scaled tunnel field-effect transistors
title_full Short-channel effect and device design of extremely scaled tunnel field-effect transistors
title_fullStr Short-channel effect and device design of extremely scaled tunnel field-effect transistors
title_full_unstemmed Short-channel effect and device design of extremely scaled tunnel field-effect transistors
title_sort short-channel effect and device design of extremely scaled tunnel field-effect transistors
publishDate 2023
url https://scholar.dlu.edu.vn/handle/123456789/2082
_version_ 1785973038823505920
spelling oai:scholar.dlu.edu.vn:123456789-20822023-12-13T04:19:38Z Short-channel effect and device design of extremely scaled tunnel field-effect transistors Nguyễn, Đăng Chiến Chun-Hsing Shih Short-Channel Effect Tunnel Field-Effect Transistor Device Design For serving as ideal switching devices in future energy-efficient applications, scaling down the channel lengths of Tunnel-Field Effect Transistors (TFETs) is essential to follow the pace of Si-based CMOS technologies. This work elucidates the short-channel mechanisms and the role of the drain in extremely-scaled TFETs. The scalability of TFETs depends strongly on the appropriately low drain concentration, whereas the capability of the drain for scaling relies on a sufficient drain region. The drain with a light concentration of 5×1017 cm-3 and a minimum length of 20nm enables 5nm TFETs to exhibit favorable on-off switching characteristics. In sub-20nm TFETs, the total drain and channel lengths must satisfy the minimum criteria of approximately 25nm to sustain reversely biased drain voltage of 0.7V. The asymmetric Si1-xGex source heterojunction is combined with the minimum drain design in 5nm TFETs to separately optimize the source- and drain-side tunnel junctions, generating ideal on-/off-currents and switching characteristics to serve as a promising design approach of sub-5nm TFETs. 55 1 31-37 2023-04-28T12:12:13Z 2023-04-28T12:12:13Z 2015 Journal article Bài báo đăng trên tạp chí thuộc ISI, bao gồm book chapter https://scholar.dlu.edu.vn/handle/123456789/2082 10.1016/j.microrel.2014.09.028 en Microelectronics Reliability 0026-2714 [1] Q. Zhang, W. Zhao, and S. A. Seabaugh. Low-subthreshold swing tunnel transistors. IEEE Electron Device Lett. 2006; 27: 297-4. [2] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. 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