Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications
This study investigates, by a two-dimensional simulation, the design optimization of a proposed 8 nm tunnel field-effect transistor (TFET) for low standby power (LSTP) applications utilizing graded Si/SiGe heterojunction with device parameters based on the ITRS specifications. The source Ge mole fra...
Gorde:
| Egile Nagusiak: | , |
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| Formatua: | Journal article |
| Hizkuntza: | English |
| Argitaratua: |
Publishing House for Science and Technology, Vietnam Academy of Science and Technology
2024
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| Gaiak: | |
| Sarrera elektronikoa: | https://scholar.dlu.edu.vn/handle/123456789/3294 |
| Etiketak: |
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| Thư viện lưu trữ: | Thư viện Trường Đại học Đà Lạt |
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