Semiconductor-thickness-dependent design of hetero-gate dielectric in double-gate TFETs
This study examined the dependence of the role and design of hetero-gate dielectric (HGD) on semiconductor film thickness in double-gate tunnel field-effect transistors (TFETs). The optimal position of the source-side dielectric heterojunction is nearly independent of the film thickness and aligned...
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IEEE Publishing
2024
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| Thư viện lưu trữ: | Thư viện Trường Đại học Đà Lạt |
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oai:scholar.dlu.edu.vn:123456789-3288 |
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Thư viện Trường Đại học Đà Lạt |
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English |
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Hetero-gate dielectric Thin film transistor Double-gate Band-to-band tunneling Tunnel field-effect transistor |
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Hetero-gate dielectric Thin film transistor Double-gate Band-to-band tunneling Tunnel field-effect transistor Nguyễn, Đăng Chiến Nguyen Van Hao Lê, Văn Tùng Chun-Hsing Shih Semiconductor-thickness-dependent design of hetero-gate dielectric in double-gate TFETs |
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This study examined the dependence of the role and design of hetero-gate dielectric (HGD) on semiconductor film thickness in double-gate tunnel field-effect transistors (TFETs). The optimal position of the source-side dielectric heterojunction is nearly independent of the film thickness and aligned with the source-channel junction. The optimal position of the drain-side dielectric heterojunction is 7.5 nm for the films thicker than 70 nm and 9.25 nm for the films thinner than 20 nm. The on-current enhancement by the HGD engineering significantly decreases with scaling the film thickness, mostly because of the gradual disappear of the local potential well due to the increase of the double-gate coupling in scaled TFETs. |
| format |
Conference paper |
| author |
Nguyễn, Đăng Chiến Nguyen Van Hao Lê, Văn Tùng Chun-Hsing Shih |
| author_facet |
Nguyễn, Đăng Chiến Nguyen Van Hao Lê, Văn Tùng Chun-Hsing Shih |
| author_sort |
Nguyễn, Đăng Chiến |
| title |
Semiconductor-thickness-dependent design of hetero-gate dielectric in double-gate TFETs |
| title_short |
Semiconductor-thickness-dependent design of hetero-gate dielectric in double-gate TFETs |
| title_full |
Semiconductor-thickness-dependent design of hetero-gate dielectric in double-gate TFETs |
| title_fullStr |
Semiconductor-thickness-dependent design of hetero-gate dielectric in double-gate TFETs |
| title_full_unstemmed |
Semiconductor-thickness-dependent design of hetero-gate dielectric in double-gate TFETs |
| title_sort |
semiconductor-thickness-dependent design of hetero-gate dielectric in double-gate tfets |
| publisher |
IEEE Publishing |
| publishDate |
2024 |
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https://scholar.dlu.edu.vn/handle/123456789/3288 |
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1798256977109843968 |
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oai:scholar.dlu.edu.vn:123456789-32882024-04-10T10:35:01Z Semiconductor-thickness-dependent design of hetero-gate dielectric in double-gate TFETs Nguyễn, Đăng Chiến Nguyen Van Hao Lê, Văn Tùng Chun-Hsing Shih Hetero-gate dielectric Thin film transistor Double-gate Band-to-band tunneling Tunnel field-effect transistor This study examined the dependence of the role and design of hetero-gate dielectric (HGD) on semiconductor film thickness in double-gate tunnel field-effect transistors (TFETs). The optimal position of the source-side dielectric heterojunction is nearly independent of the film thickness and aligned with the source-channel junction. The optimal position of the drain-side dielectric heterojunction is 7.5 nm for the films thicker than 70 nm and 9.25 nm for the films thinner than 20 nm. The on-current enhancement by the HGD engineering significantly decreases with scaling the film thickness, mostly because of the gradual disappear of the local potential well due to the increase of the double-gate coupling in scaled TFETs. 2024-03-01T03:03:59Z 2024-03-01T03:03:59Z 2021 Conference paper Bài báo đăng trên KYHT quốc tế (có ISBN) https://scholar.dlu.edu.vn/handle/123456789/3288 10.1109/ICCE48956.2021.9352038 en Nghiên cứu và thiết kế các transistor trường xuyên hầm với cấu trúc điện môi cực cổng dị chất IEEE Eighth International Conference on Communications and Electronics (ICCE) B2019-DLA-05 [1] L. Knoll, M. Schmidt, Q. T. Zhao, S. Trellenkamp, A. Schafer, K. K. Bourdelle, and S. Mantl, “Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped NiSi2 tunnel junctions,” Solid-State Electron., vol. 84, pp. 211-215, Jun. 2013. [2] H. Fuketa, K. Yoshioka, K. Fukuda, T. Mori, H. Ota, M. Takamiya, T. Sakurai, “Design guidelines to achieve minimum energy operation for ultra low voltage tunneling FET logic circuits,” Jpn. J. Appl. Phys., vol. 54, p. 04DC04, Apr. 2015. [3] L. Knoll, M. Schmidt, Q. T. Zhao, S. Trellenkamp, A. Schafer, K. K. Bourdelle, S. Mantl, “Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped NiSi2 tunnel junctions,” Solid-State Electron., vol. 84, pp. 211-215, Jun. 2013. [4] IEEE International Roadmap for Devices and Systems (IRDS), 2018. [Online] Available at: http://irds.ieee.org/. [5] O. M. Nayfeh, J. L. Hoyt, D. A. Antoniadis, “Strained-Si1-xGex/Si band-to-band tunneling transistors: Impact of tunnel junction germanium composition and doping concentration on switching behavior,” IEEE Trans. Electron Devices, vol. 56, pp. 2264-2269, Oct. 2009. [6] S. B. Rahi, P. Asthana, S. Gupta, “Heterogate junctionless tunnel field-effect transistor: future of low-power devices,” J. Comput. Electron., vol. 16, pp. 30-38, Mar. 2017. [7] N. D. Chien, C.-H. Shih, L. T. Vinh, “Drive current enhancement in tunnel field-effect transistors by graded heterojunction approach,” J. Appl. Phys., vol. 114, p. 094507, Sep. 2013. [8] J. Talukdar, K. Mummaneni, “A non-uniform silicon TFET design with dual-material source and compressed drain,” Appl. Phys. A, vol. 126, p. 81, Jan. 2020. [9] N. D. Chien, C.-H. Shih, “Oxide thickness-dependent effects of source doping profile on the performance of single- and double-gate tunnel field-effect transistors,” Superlattices Microstruct., vol. 102, pp. 284-99, Feb. 2017. [10] M. R. U. Shaikh, S. A. Loan, “Drain-engineered TFET with fully suppressed ambipolarity for high-frequency application,” IEEE Trans. Electron Devices, vol. 66, pp. 1628-1634, Apr. 2019. [11] N. D. Chien, C.-H. Shih, Y.-H. Chen, N. T. Thu, “Increasing drain voltage of low-bandgap tunnel field-effect transistors by drain engineering,” in Proc. of Int. Conf. on Electronics, Information and Communication (ICEIC), Vietnam, 2016, pp. 10-13. [12] W.-Y. Choi, W. Lee, “Hetero-gate-dielectric tunneling field-effect transistors,” IEEE Trans. Electron Devices, vol. 57, pp. 2317-2319, Sep. 2010. [13] W.-Y. Choi, H. K. Lee, “Demonstration of hetero-gate-dielectric tunneling field-effect transistors,” Nano Convergence, vol. 3, p. 13, Jun. 2016. [14] C.-H. Shih, N. D. Chien, H.-D. Tran, P. V. Chuan, “Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low/high-k EOT ratios,” Appl. Phys. A, vol. 126, p. 66, Jan. 2020. [15] 2013 Synopsys MEDICI User’s Manual (California: Synopsys Inc.) [16] E. O. Kane, “Theory of tunneling,” J. Appl. Phys., vol. 31, pp. 83-91, Jan. 1961. [17] Q. Smet et al., “InGaAs tunnel diodes for the calibration of semi-classical and quantum mechanical band-to-band tunneling models,” J. Appl. Phys., vol. 115, p. 184503, Apr. 2014. IEEE Publishing USA |