On-current limitation of high-k gate insulator MOSFETs

This work explores the limitation of high-k gate insulator on improving the driving currents of MOSFET devices. The use of high-k gate dielectric prevents from the gate tunneling current to have an acceptable equivalent oxide thickness (EOT) in scaled MOSFETs. However, the effectiveness of continued...

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Những tác giả chính:	Chun-Hsing Shih, Jhong-Sheng Wang, Nguyễn, Đăng Chiến, Ruei-Kai Shia
Định dạng:	Journal article
Ngôn ngữ:	English
Được phát hành:	Elsevier 2024
Những chủ đề:	High-k gate insulator MOSFETs Inversion layer thickness
Truy cập trực tuyến:	https://scholar.dlu.edu.vn/handle/123456789/3296
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id	oai:scholar.dlu.edu.vn:123456789-3296
record_format	dspace
institution	Thư viện Trường Đại học Đà Lạt
collection	Thư viện số
language	English
topic	High-k gate insulator MOSFETs Inversion layer thickness
spellingShingle	High-k gate insulator MOSFETs Inversion layer thickness Chun-Hsing Shih Jhong-Sheng Wang Nguyễn, Đăng Chiến Ruei-Kai Shia On-current limitation of high-k gate insulator MOSFETs
description	This work explores the limitation of high-k gate insulator on improving the driving currents of MOSFET devices. The use of high-k gate dielectric prevents from the gate tunneling current to have an acceptable equivalent oxide thickness (EOT) in scaled MOSFETs. However, the effectiveness of continued EOT reduction in strengthening gate control is limited strongly by the non-scalability of the quantum effect of inversion layer thickness. Both classical and quantum–mechanical approaches of inversion layer thickness are presented to study the effective gate capacitances and associated on-state drain currents. The enhancements of drain current and gate capacitance generated by high-k gate dielectrics are gradually saturated when a higher permittivity dielectric is applied.
format	Journal article
author	Chun-Hsing Shih Jhong-Sheng Wang Nguyễn, Đăng Chiến Ruei-Kai Shia
author_facet	Chun-Hsing Shih Jhong-Sheng Wang Nguyễn, Đăng Chiến Ruei-Kai Shia
author_sort	Chun-Hsing Shih
title	On-current limitation of high-k gate insulator MOSFETs
title_short	On-current limitation of high-k gate insulator MOSFETs
title_full	On-current limitation of high-k gate insulator MOSFETs
title_fullStr	On-current limitation of high-k gate insulator MOSFETs
title_full_unstemmed	On-current limitation of high-k gate insulator MOSFETs
title_sort	on-current limitation of high-k gate insulator mosfets
publisher	Elsevier
publishDate	2024
url	https://scholar.dlu.edu.vn/handle/123456789/3296
_version_	1798256981323022336
spelling	oai:scholar.dlu.edu.vn:123456789-32962024-03-01T07:41:17Z On-current limitation of high-k gate insulator MOSFETs Chun-Hsing Shih Jhong-Sheng Wang Nguyễn, Đăng Chiến Ruei-Kai Shia High-k gate insulator MOSFETs Inversion layer thickness This work explores the limitation of high-k gate insulator on improving the driving currents of MOSFET devices. The use of high-k gate dielectric prevents from the gate tunneling current to have an acceptable equivalent oxide thickness (EOT) in scaled MOSFETs. However, the effectiveness of continued EOT reduction in strengthening gate control is limited strongly by the non-scalability of the quantum effect of inversion layer thickness. Both classical and quantum–mechanical approaches of inversion layer thickness are presented to study the effective gate capacitances and associated on-state drain currents. The enhancements of drain current and gate capacitance generated by high-k gate dielectrics are gradually saturated when a higher permittivity dielectric is applied. 78 Selected Papers from ISDRS 2011 87-91 2024-03-01T07:41:12Z 2024-03-01T07:41:12Z 2012 Journal article Bài báo đăng trên tạp chí thuộc ISI, bao gồm book chapter https://scholar.dlu.edu.vn/handle/123456789/3296 10.1016/j.sse.2012.05.046 en Solid-State Electronics 0038-1101 [1] ITRS, International Technology Roadmap for Semiconductor; 2009. [2] Mistry K, Allen C, Auth C, Beattie B, Bergstrom D, Bost M, et al. A 45 nm logic technology with high-k+metal gate transistors, strained silicon, Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. in: IEDM, December 2007. p. 247–50. [3] Chudzik M, Doris B, Mo R, Sleight J, Cartier E, Dewan C. High-performance high-k/metal gates for 45 nm CMOS and beyond with gate-first processing. in: VLSI, June 2007. p. 194–5. [4] Hobbs C, Fonseca L, Dhandapani V, Samavedam S, Taylor B, Grant J, et al. Fermi level pinning at the poly Si/metal oxide interface. in: VLSI, June 2003. p. 9–10. [5] Shiraishi K, Takeuchi H, Akasaka Y, Watanabe H, Umezawa N, Chikyow T. Theory of fermi level pinning of high-k dielectrics. in: ISSPD, September 2006. p. 306–13. [6] Xiong K, Peacock PW, Robertson J. Fermi level pinning and Hf–Si bonds at HfO2: polycrystalline silicon gate electrode interfaces. Appl Phys Lett Jan. 2005;86:102904. [7] Fischetti MV, Neumayer DA, Cartier EA. Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high-k insulator: the role of remote phonon scattering. J Appl Phys 2001;90:4587–608. [8] Datta S, Dewey G, Doczy M, Doyle BS, Jin B, Kavalieros J. High mobility Si/SiGe strained channel MOS transistors with HfO2/TiN gate stack. in: IEDM, December 2003. p. 28.1.1–28.1.4. [9] Bhatt AR, Kim KW, Stroscio MA, Iafrate GJ, Dutta Mitra, Grubin Harold L, et al. Reduction of interface phonon modes using metal-semiconductor heterostructures. J Appl Phys 1993;73:2338–42. [10] Chau R, Datta S, Doczy M, Doyle B, Kavalieros J, Metz M. High-/metal-gate stack and its MOSFET characteristics. IEEE Electron Device Lett 2004;25:408–10. [11] Hauser JR. A new and improved physics-based model for MOS transistors. IEEE Trans Electron Dev 2005;52:2640–7. [12] Katto H. A compact and accurate MOSFET model with simple expressions for linear, saturation and sub-threshold regions. Solid-State Electron 2006;50:301–8. [13] Kloes A. Unified current equation for predictive modeling of submicron MOSFETs. Solid-State Electron 2005;49:85–95. [14] Lallement C, Sallese J-M, Bucher M, Grabinski W, Fazan PC. Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model. IEEE Trans Electron Dev 2003;50:406–17. [15] Jayadeva GS, DasGupta Amitava. Compact model of short-channel MOSFETs considering quantum mechanical effects. Solid-State Electron 2009;53:649–56. [16] Pregaldiny Fabien, Lallement Christophe, Mathiot Daniel. Accounting for quantum mechanical effects from accumulation to inversion, in a fully analytical surface potential-based MOSFET model. Solid-State Electron 2004;48:781–7. [17] MEDICI User‘s Manual, Synopsys, Fremont, CA; 2006. [18] Taur Y, Ning TH. Fundamentals of modern VLSI devices. 2nd ed., Cambridge; 2009. [19] Brews JR. A charge sheet model for the MOSFET. Solid-State Electron 1978;21:345–55. [20] Stern F. Self-consistent results for n-type Si inversion layers. Phys Rev B 1972;5:4891–9. [21] Hensel JC, Hasegawa H, Nakayama M. Cyclotron resonance in uniaxially stressed silicon. II. Nature of the covalent bond. Phys Rev 1965;138:A225–38. Elsevier Netherlands

On-current limitation of high-k gate insulator MOSFETs

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