Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors

In this study, we examined the influence of using hetero-gate dielectrics (HGDs) on the short-channel effects (SCEs) in scaled tunnel field-effect transistors (TFETs). For bulk TFETs, the short-channel performance is not influenced by the HGD engineering because the SCEs are caused by the tunneling...

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Những tác giả chính: Nguyễn, Đăng Chiến, Luu The Vinh, Huynh Thi Hong Tham, Chun-Hsing Shih
Định dạng: Journal article
Ngôn ngữ:English
Được phát hành: Elsevier 2024
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Truy cập trực tuyến:https://scholar.dlu.edu.vn/handle/123456789/3289
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id oai:scholar.dlu.edu.vn:123456789-3289
record_format dspace
institution Thư viện Trường Đại học Đà Lạt
collection Thư viện số
language English
topic Short-channel effect
Hetero-gate dielectric
Band-to-band tunneling
Double-gate
Tunnel field-effect transistor
spellingShingle Short-channel effect
Hetero-gate dielectric
Band-to-band tunneling
Double-gate
Tunnel field-effect transistor
Nguyễn, Đăng Chiến
Luu The Vinh
Huynh Thi Hong Tham
Chun-Hsing Shih
Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors
description In this study, we examined the influence of using hetero-gate dielectrics (HGDs) on the short-channel effects (SCEs) in scaled tunnel field-effect transistors (TFETs). For bulk TFETs, the short-channel performance is not influenced by the HGD engineering because the SCEs are caused by the tunneling at the region with negligible gate control. However, the use of the HGD increases the SCEs in double-gate TFETs because the HGD reduces the gate control on the channel. When the HGD optimized in term of on-current is used, the channel of HGD-TFETs is about 10-nm longer than that of uniform-gate dielectric TFETs to obtain similar SCEs. The SCEs in HGD-TFETs can be improved by locating the drain-side heterojunction toward the drain and/or increasing the ratio of low- and high-k equivalent oxide thicknesses. Due to the trend of scaling transistors, an appropriate design of HGD to minimize the SCEs in scaled HGD-TFETs is also crucial.
format Journal article
author Nguyễn, Đăng Chiến
Luu The Vinh
Huynh Thi Hong Tham
Chun-Hsing Shih
author_facet Nguyễn, Đăng Chiến
Luu The Vinh
Huynh Thi Hong Tham
Chun-Hsing Shih
author_sort Nguyễn, Đăng Chiến
title Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors
title_short Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors
title_full Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors
title_fullStr Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors
title_full_unstemmed Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors
title_sort influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors
publisher Elsevier
publishDate 2024
url https://scholar.dlu.edu.vn/handle/123456789/3289
_version_ 1798256977517740032
spelling oai:scholar.dlu.edu.vn:123456789-32892024-03-01T03:31:28Z Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors Nguyễn, Đăng Chiến Luu The Vinh Huynh Thi Hong Tham Chun-Hsing Shih Short-channel effect Hetero-gate dielectric Band-to-band tunneling Double-gate Tunnel field-effect transistor In this study, we examined the influence of using hetero-gate dielectrics (HGDs) on the short-channel effects (SCEs) in scaled tunnel field-effect transistors (TFETs). For bulk TFETs, the short-channel performance is not influenced by the HGD engineering because the SCEs are caused by the tunneling at the region with negligible gate control. However, the use of the HGD increases the SCEs in double-gate TFETs because the HGD reduces the gate control on the channel. When the HGD optimized in term of on-current is used, the channel of HGD-TFETs is about 10-nm longer than that of uniform-gate dielectric TFETs to obtain similar SCEs. The SCEs in HGD-TFETs can be improved by locating the drain-side heterojunction toward the drain and/or increasing the ratio of low- and high-k equivalent oxide thicknesses. Due to the trend of scaling transistors, an appropriate design of HGD to minimize the SCEs in scaled HGD-TFETs is also crucial. 20 12 1342-1350 2024-03-01T03:31:24Z 2024-03-01T03:31:24Z 2020 Journal article Bài báo đăng trên tạp chí thuộc ISI, bao gồm book chapter https://scholar.dlu.edu.vn/handle/123456789/3289 10.1016/j.cap.2020.09.004 en Nghiên cứu và thiết kế các transistor trường xuyên hầm với cấu trúc điện môi cực cổng dị chất Current Applied Physics 1567-1739 B2019-DLA-05 [1] W.Y. Choi, B.-G. Park, J.D. Lee, T.-J.K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron Device Lett. 28 (2007) 743-745. [2] J.-S. Liu, M.B. Clavel, M.K. Hudait, TBAL: Tunnel FET-based adiabatic logic for energy-efficient, ultra-low voltage IoT applications, IEEE J. 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