Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications

Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications

This study investigates, by a two-dimensional simulation, the design optimization of a proposed 8 nm tunnel field-effect transistor (TFET) for low standby power (LSTP) applications utilizing graded Si/SiGe heterojunction with device parameters based on the ITRS specifications. The source Ge mole fra...

Mô tả đầy đủ

Đã lưu trong:
Chi tiết về thư mục
Những tác giả chính: Nguyễn, Đăng Chiến, Luu The Vinh
Định dạng: Journal article
Ngôn ngữ:English
Được phát hành: Publishing House for Science and Technology, Vietnam Academy of Science and Technology 2024
Những chủ đề:
Graded Si/SiGe
Low standby power (LSTP)
Short-channel device
Tunnel field-effect transistor
Truy cập trực tuyến:https://scholar.dlu.edu.vn/handle/123456789/3294
Các nhãn: Thêm thẻ
Không có thẻ, Là người đầu tiên thẻ bản ghi này!
Thư viện lưu trữ: Thư viện Trường Đại học Đà Lạt
id oai:scholar.dlu.edu.vn:123456789-3294
record_format dspace
institution Thư viện Trường Đại học Đà Lạt
collection Thư viện số
language English
topic Graded Si/SiGe
Low standby power (LSTP)
Short-channel device
Tunnel field-effect transistor
spellingShingle Graded Si/SiGe
Low standby power (LSTP)
Short-channel device
Tunnel field-effect transistor
Nguyễn, Đăng Chiến
Luu The Vinh
Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications
description This study investigates, by a two-dimensional simulation, the design optimization of a proposed 8 nm tunnel field-effect transistor (TFET) for low standby power (LSTP) applications utilizing graded Si/SiGe heterojunction with device parameters based on the ITRS specifications. The source Ge mole fraction should be designed approximately 0.8 because using lower Ge fractions causes severe short-channel effects while with higher values does not significantly improve the device performance but may create big difficulties in fabrication. Based on simultaneously optimizing the subthreshold swing, on- and off-currents, optimum values of source doping, drain doping and length of the proposed device are approximately 1020 cm-3, 1018 cm-3, and 10 nm, respectively. The 8 nm graded Si/SiGe TFET with optimized device parameters demonstrates high on-current of 360 μA/μm, low off-current of 0.5 pA/μm, low threshold voltage of 85 mV and very steep subthreshold swing of sub-10 mV/decade. The designed TFET with graded Si/SiGe heterojunction exhibits an excellent performance and makes it an attractive candidate for future LSTP technologies because of its reality to be fabricated with existing FET and SiGe growth techniques.
format Journal article
author Nguyễn, Đăng Chiến
Luu The Vinh
author_facet Nguyễn, Đăng Chiến
Luu The Vinh
author_sort Nguyễn, Đăng Chiến
title Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications
title_short Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications
title_full Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications
title_fullStr Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications
title_full_unstemmed Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications
title_sort design optimization of extremely short-channel graded si/sige heterojunction tunnel field-effect transistors for low power applications
publisher Publishing House for Science and Technology, Vietnam Academy of Science and Technology
publishDate 2024
url https://scholar.dlu.edu.vn/handle/123456789/3294
_version_ 1798256980183220224
spelling oai:scholar.dlu.edu.vn:123456789-32942024-03-01T07:19:43Z Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications Nguyễn, Đăng Chiến Luu The Vinh Graded Si/SiGe Low standby power (LSTP) Short-channel device Tunnel field-effect transistor This study investigates, by a two-dimensional simulation, the design optimization of a proposed 8 nm tunnel field-effect transistor (TFET) for low standby power (LSTP) applications utilizing graded Si/SiGe heterojunction with device parameters based on the ITRS specifications. The source Ge mole fraction should be designed approximately 0.8 because using lower Ge fractions causes severe short-channel effects while with higher values does not significantly improve the device performance but may create big difficulties in fabrication. Based on simultaneously optimizing the subthreshold swing, on- and off-currents, optimum values of source doping, drain doping and length of the proposed device are approximately 1020 cm-3, 1018 cm-3, and 10 nm, respectively. The 8 nm graded Si/SiGe TFET with optimized device parameters demonstrates high on-current of 360 μA/μm, low off-current of 0.5 pA/μm, low threshold voltage of 85 mV and very steep subthreshold swing of sub-10 mV/decade. The designed TFET with graded Si/SiGe heterojunction exhibits an excellent performance and makes it an attractive candidate for future LSTP technologies because of its reality to be fabricated with existing FET and SiGe growth techniques. 51 6 757–768 2024-03-01T07:19:38Z 2024-03-01T07:19:38Z 2013 Journal article Bài báo đăng trên tạp chí trong nước (có ISSN), bao gồm book chapter https://scholar.dlu.edu.vn/handle/123456789/3294 10.15625/2525-2518/51/6/11642 en Vietnam Journal of Science and Technology 2525-2518 1. Wang P. F., Hilsenbeck K., Nirschl Th., Oswald M., Stepper Ch., Weis M., Schmitt-Landsiedel D., and Hansch W. - Complementary tunneling transistor for low power application, Solid-State Electron. 48 (2004) 2281-2286. 2. Bhuwalka K. K., Schulze J., and Eisele I. - Performance enhancement of vertical tunnel field-effect transistor with SiGe in the layer, Jpn. J. Appl. Phys. 43 (2004) 4073-4078. 3. Choi W. Y., Park B.-G., Lee J. D., and Liu T.-J. K. - Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron Device Lett. 28 (2007) 743-745. 4. Toh E.-H., Wang G. H., Chan L., Sylvester D., Heng C.-H., Samudra G. S., and Yeo Y.-C. - Device design and scalability of a double-gate tunneling field-effect transistor with silicon–germanium source, Jpn. J. Appl. Phys. 47 (2008) 2593-2597. 5. Wang L., Yu E., Taur Y., and Asbeck P. - Design of tunneling field-effect transistors based on staggered heterojunctions for ultralow-power applications, IEEE Electron Device Lett. 31 (2010) 431-433. 6. International Technology Roadmap for Semiconductor (ITRS), 2011 edition (available at http://www.itrs.net/). 7. Bhuwalka K., Born M., Schindler M., Schmidt M., Sulima T., and Eisele I. - P-Channel tunnel field-effect transistors down to sub-50 nm channel lengths, Jpn. J. Appl. Phys. 45 (2006) 3106-3109. 8. Mookerjea S. and Datta S. - Comparative study of Si, Ge and InAs based steep subthreshold slope tunnel transistors for 0.25V supply voltage logic applications, Tech. Dig. of the 66th Device Research Conference 2008, 47-48. 9. Kane E. O. - Zener tunneling in semiconductors, J. Phys. Chem. Solids 12 (1960) 181-188. 10. Nayfeh O. M., Hoyt J. L., and Antoniadis D. A. - Strained-Si1-xGex/Si Band-to-Band Tunneling Transistors: Impact of Tunnel Junction Germanium Composition and Doping Concentration on Switching Behavior, IEEE Trans. Electron Devices 56 (2009) 2264-2269. 11. Ford A. C., Yeung C. W., Chuang S., Kim H. S., Plis E., Krishna S., Hu C., and Javey A. - Ultrathin body InAs tunneling field-effect transistors on Si substrates, Appl. Phys. Lett. 98 (2011) 113105-113105-3. 12. Boucart K. and Ionescu A. M. - Length scaling of the double gate tunnel FET with a high-k gate dielectric, Solid State Electron. 51 (2007) 1500-1507. 13. Khatami Y. and Banerjee K. - Scaling analysis of Graphene Nanoribbon tunnel-FETs, Device Research Conference (DRC), 2009, pp.197-198. 14. Bardon M. G., Neves H. P., Puers R., and Hoof C. V. - Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions, IEEE Trans. Electron Devices 57 (2010) 827-834. 15. Boucart K. and Ionescu A. M. - Double-gate tunnel FET with high-κ gate dielectric, IEEE Trans. Electron Devices 54 (2007) 1725-1733. 16. Krishnamohan T., Donghyun K., Raghunathan S., and Saraswat K. - Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and < 60 mV/dec subthreshold slope, IEEE International Electron Devices Meeting (IEDM), 2008, pp. 1-3. 17. Verhulst A. S., Vandenberghe W. G., Maex K., and Groeseneken G. - Tunnel field-effect transistor without gate-drain overlap, Appl. Phys. Lett. 91 (2007) 053102-053102-3. 18. Chattopadhyay A. and Mallik A. - Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor, IEEE Trans. Electron Devices 58 (2011) 677-683. 19. Cui N., Liang R., and Xu J. - Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation, Appl. Phys. Lett. 98 (2011) 142105-142105-3. 20. Toh E. H., Wang G. H., Samudra G., and Yeo Y. C. - Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications, J. Appl. Phys. 103 (2008) 104504-104504-5. 21. Shih C.-H. and Chien N. D. - Sub-10-nm tunnel field-effect transistor with graded Si/Ge heterojunction, IEEE Electron Device Lett. 32 (2011) 1498-1500. 22. Synopsys MEDICI User’s Manual, Synopsys Inc., Mountain View, CA, 2010. 23. Toh E. H., Wang G. H., Samudra G., and Yeo Y. C. - Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization, Appl. Phys. Lett. 90 (2007) 263507-263507-3. 24. Bhuwalka K. K., Schulze J., and Eisele I. - A simulation approach to optimize the electrical parameters of a vertical tunnel FET, IEEE trans. Electron Devices 52 (2005) 1541-1547. 25. Loh W. Y., Jeon K., Kang C. Y., Oh J., Liu T. J. K., Tseng H. H., Xiong W., Majhi P., Jammy R., and Hu C. - Highly scaled (Lg 56 nm) gate-last Si tunnel field-effect transistors with ION 100 μAμm, Solid-State Electron. 65-66 (2011) 22-27. 26. Reddik W. M. and Amaratunga G. A. J. - Gate controlled surface tunneling transistor, High Speed Semiconductor Dev. Circuits, 1995, pp. 490-497. 27. Kim D., Krishnamohan T., Smith L., Wong H.-S. P., and Saraswat K. C. - Band to band tunneling study in high mobility materials: III-V, Si, Ge and strained SiGe, the 65th Annual Device Research Conference (DRC) 2007, pp. 57-58. 28. Han G., Guo P., Yang Y., Fan L., Yee Y. S., Zhan C., and Yeo Y.-C. - Source engineering for tunnel field-effect transistor: elevated source with vertical silicon-germanium/germanium heterojunction, Jpn. J. Appl. Phys. 50 (2011) 04DJ07-04DC05-4. 29. Virani H. G., Rao R. B., and Kottantharayil A. - Investigation of novel Si-SiGe heterostructures and Gate induced source tunneling for improvement of p-channel tunnel field-effect transistors, Jpn. J. Appl. Phys. 49 (2010) 04DC12-04DC12-5. 30. Leonelli D., Vandooren A., Rooyackers R., Verhulst A. S., Gendt S. D., Heyns M. M., and Groeseneken G. - Silicide engineering to boost Si tunnel transistor drive current, Jpn. J. Appl. Phys. 50 (2011) 04DC05-04DC05-4. 31. Wang K. L. and Karunasiri R. P. G. - SiGe/Si electronics and optoelectronics, J. Vac. Sci. Technol. B 11 (1993) 1159-1167. 32. Kim K. and Lee Y. H. - Temperature-dependent critical layer thickness for strained-layer heterostructures, Appl. Phys. Lett. 67 (1995) 2212-2214. 33. Chung T. M., Olbrechts B., Sodervall U., Bengtsson S., Flandre D., and Raskin J.-P. - Planar double-gate SOI MOS devices-fabrication by wafer bonding over pre-patterned cavities and electrical characterization, Solid-State Electron. 51 (2007) 231-238. Publishing House for Science and Technology, Vietnam Academy of Science and Technology Việt Nam

Những quyển sách tương tự